Patent Literature 1 (see FIG. 34) discloses a configuration in which an output of each stage of a shift register included in a gate driver is supplied to an NAND circuit, and a DCG signal is also supplied to the NAND circuit. Moreover, an output of the NAND circuit is supplied to a corresponding scanning signal line. With the configuration, by causing the DCG signal to be active when a power supply of a liquid crystal display device is turned on or off, it is possible to simultaneously select all the scanning signal lines so that a Vcom (common electrode electric potential) is written into all pixels.
Patent Literature 2 (see FIG. 35) discloses a gate driver which includes a shift register having a plurality of stages. Each of the plurality of stages has (i) a set-reset type flip-flop and (ii) a gate circuit including an analog switch 43 and an n-channel transistor 45. Moreover, a clock signal CK is supplied to the analog switch 43, a source of an n-channel transistor 44 is connected to a VSS, and an output of each of the stages is supplied to a corresponding scanning signal line. In the configuration, when a power supply of a liquid crystal display device is turned on or off, output signals of all the stages become active by causing a setting signal to the first stage of the shift register to become active while the clock signal CK is being fixedly active. This makes it possible to simultaneously select all the scanning signal lines so that a Vcom (common electrode electric potential) is written into all pixels.